The invention relates to a signal generating circuit and a method for activating a physical channel between a host and a peripheral device, and more particularly, to the signal generating circuit and related method for activating the physical channel between the host and the peripheral device without the help of a microprocessor disposed in the peripheral device.
Serial advanced technology attachment (SATA) specifications are applied to a transmission interface between a host and a peripheral device, such as a hard disk drive or an optical disc drive. SATA specifications define two pairs of differential signals, which are different from the forty or eighty parallelized signals in the advanced technology attachment (ATA) specifications. When a system utilizes the SATA interface to communicate with other devices, the system would have the advantages of less pin counts, lower operation voltages and higher transmission rate. SATA specifications also include some new functions, such as flow control and retransmission, to perform simple control on a data stream.
Referring to FIG. 1, which is a schematic diagram of out of band (OOB) signals specified in the SATA specifications. SATA specifications specify three OOB signals, which are COMRESET, COMINIT and COMWAKE, to make sure the differential and common levels of the signal lines shall comply with the SATA specifications for in-band data transmission. After the OOB sequence is completed, the communication link is established and normal operation may begin. And it is a state defined as Phy Ready state. When entering the Phy Ready state, the host and the peripheral device corresponding to two different sides of the physical channel are maintained to be synchronized with each other so that signals transmitted from one side of the physical channel are also valid to the other side of the physical channel.
Please refer to FIG. 2 and FIG. 3 simultaneously. FIG. 2 is a host-to-device register FIS structure according to SATA standards while FIG. 3 is a device-to-host register FIS structure according to SATA standards. As the Phy Ready state mentioned above is achieved, the host is specifically prohibited from writing the Features, Sector Count, Sector Number, Cylinder Low, Cylinder High, or Device/Head registers, whose corresponding fields defined in a register FIS can be found on FIG. 2 and FIG. 3, until the peripheral device replies Register FIS to clear either value in BSY or DRQ field in the Status Register. Any writing to the Command Register when BSY or DRQ field is set is ignored unless the writing is to issue a Device Reset command. Please note that, according to the SATA specifications, BSY is set when the peripheral device is busy and is not available temporarily to the host while DRQ is set when the peripheral device is ready to transfer a word or byte of data between the host and the peripheral device.
Therefore, without Register FIS transmitted from the peripheral device to the host, the host will not be able to request the peripheral device to perform any operation and the peripheral device would be seemed as not available. Generally speaking, this is a status response problem and is usually performed under the control of firmware. Thus, to write the firmware through a SATA differential channel from a host to a peripheral device under the condition that the firmware is not available in the peripheral device, this status response problem must be overcame first.